Teknik Belgeler
Özellikler
Marka
NexperiaÜrün Tipi
Kaymalı Kaydedici
Montaj Tipi
Yüzey
Maksimum Besleme Gerilimi
6V
Minimum Çalışma Sıcaklığı
-40°C
Maksimum Çalışma Sıcaklığı
125°C
Standartlar/Onaylar
RoHS
Ürün Ayrıntıları
The 74HC4094, 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.
Stok bilgileri geçici olarak kullanılamıyor.
1.300,20 TL
26,004 TL Each (In a Tube of 50) (KDV Hariç)
1.560,24 TL
31,205 TL Each (In a Tube of 50) KDV Dahil
50
1.300,20 TL
26,004 TL Each (In a Tube of 50) (KDV Hariç)
1.560,24 TL
31,205 TL Each (In a Tube of 50) KDV Dahil
Stok bilgileri geçici olarak kullanılamıyor.
50
| Miktar | Birim Fiyat | Per Tüp |
|---|---|---|
| 50 - 50 | 26,004 TL | 1.300,20 TL |
| 100 - 200 | 23,76 TL | 1.188,00 TL |
| 250 - 450 | 23,232 TL | 1.161,60 TL |
| 500 - 950 | 22,638 TL | 1.131,90 TL |
| 1000+ | 22,044 TL | 1.102,20 TL |
Teknik Belgeler
Özellikler
Marka
NexperiaÜrün Tipi
Kaymalı Kaydedici
Montaj Tipi
Yüzey
Maksimum Besleme Gerilimi
6V
Minimum Çalışma Sıcaklığı
-40°C
Maksimum Çalışma Sıcaklığı
125°C
Standartlar/Onaylar
RoHS
Ürün Ayrıntıları
The 74HC4094, 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.